Design-Reuse

The Challenges and Benefits of Analog/Mixed-Signal and RF System Verification above the Transistor Level

Abstract— Today’s on-chip Analog/Mixed-Signal and RF (A/RF) systems have reached a limit of size and complexity where transistor-level SPICE and FastSPICE simulation approaches cannot deliver a ...
Electronic Design

Formal Verification Tools Check SoCs Down To Transistor Level

Targeted for users of next-generation physical design closure tools, customer-owned tooling (COT) flows, and advanced ASIC flows, a new suite of formal verification products reaches into the physical ...
Semiconductor Engineering

Overcoming Low Power Verification Challenges For Mixed-Signal SoC Designs

Isolation, retention, and power switches are the important functionalities of power-aware designs which use the common low power techniques like power shutoff, multi-voltage, and advanced techniques ...
Electronic Design

Pre-Layout Tool Boosts Yield For Analog Circuits

Greater amounts of RF and analog/mixed-signal circuitry are wending their way into SoC designs, often producing headaches for designers on a number of levels. First off, analog is just plain hard to ...
Design-Reuse

Automated Transistor-Level Optimization in Standard-Cell Based Digital Design

As feature sizes continue to shrink at a breakneck pace, transistor-level analysis and optimization in digital design is becoming a necessity for achieving a solution with the unique combination of ...