Electronic Design

Clock IC Harnesses GPS Signal For Synchronization

The AD9548 clock generator/synthesizer is the first clock IC that lets designers use the standard, free 1-pulse/s signal of GPS satellites to generate and synchronize clock signals for communications ...
Semiconductor Engineering

The Design Challenges Of Clock Integrity And Clock Jitter

Races, missed next-state values due to long paths, and metastability can result from corrupted clock signals. This post describes the challenges of clock network and clock jitter analysis in more ...
EDN

Analog/mixed-signal IC design evolves to meet new challenges

In the analog/mixed-signal (AMS) arena, automated design of advanced ICs has long remained an objective rather than a reality. For the AMS design expert, automated tools have too often seemed to ...
EDN

Introducing the Integrated Circuit (IC) Design Cycle

The process of designing, manufacturing, and testing ICs is complex and exhaustive. The main contributors are the design and verification teams, IP vendors, and IC manufacturers. The process of ...
Electronic Design

Timing Decisions 102: Optimize Your Clock Tree

The importance of timing requirements and jitter budgets for FPGAs, ASICs, and SoCs. How to utilize the information portrayed in a clock tree to choose the most well-suited clock generator for your ...
Semiconductor Engineering

Conquer Placement And Clock Tree Challenges In HPC Designs

High-performance computing (HPC) applications require IC designs with maximum performance. However, as process technology advances, achieving high performance has become increasingly challenging.