EDN

Flex Logix High-Performance Embedded FPGA IP Core Now Available for TSMC 16FF+ and 16FFC

“Configurable-cloud data centers will change the world with their ability to reprogram a data center's hardware protocols: networking, storage and security,” said Geoff Tate, CEO and co-founder of ...
Electronic Design

22nm 3D Transistor FPGA Packs In Hard Core IP

Achronix Semiconductor's latest Speedster FPGA is packed full of hard core interfaces such as PCI Express. It is based on Intel's 3D 22nm FinFET transistors and targets high performance applications ...
CU Boulder News & Events

ECEA 5362 FPGA Softcore Processors and IP Acquisition

The objective of this course is to learn how to develop, program, and use Softcore Processors with associated IP integration. To accomplish this, the Nios II Softcore Processor from Intel Altera is ...
EDN

Web-Based IP Core Evaluation Program for FPGA

Actel Corporation unveiled its new Web-based intellectual property (IP) evaluation program, which allows customers to access and download free evaluation versions of cores from Actel's broad IP ...
Business Wire

PRO DESIGN Introduces Zynq™ UltraScale+™ Based FPGA SoC and IP Prototyping Platform

MUNICH--(BUSINESS WIRE)--PRO DESIGN, a leading supplier of FPGA-based Prototyping systems, today announced the launch of its three new proFPGA Zynq™ UltraScale+™ FPGA modules, which offer a complete ...
Embedded

Basics of core-based FPGA design: Part 2 – System design considerations

There are a number of system design factors requiring consideration when implementing an FPGA processor. Some of those factors include the use of co-design, processor architectural implementation, ...
Business Wire

intoPIX Unveils Latest JPEG XS FPGA Cores with Nextera-Adeas ST2110/IPMX, Streamlining IPMX Development at NAB Show

MONT-SAINT-GUIBERT, Belgium--(BUSINESS WIRE)--intoPIX, a pioneering provider of lightweight compression solutions, is thrilled to announce its collaboration with Nextera Video and Adeas showcasing the ...
Design-Reuse

Lattice Announces Immediate Availability of DDR SDRAM Controller IP Core for LatticeECP and LatticeEC FPGA Families

Pipelined Intellectual Property Core Validated In-System At 200MHz/400DDR; Designed For High-Speed Operation Using Embedded DDR Support In LatticeECP/LatticeEC FPGA Devices The Double Data Rate (DDR) ...
Design-Reuse

Nuvation Introduces GEOS 2+2 IP Core

SAN JOSE, CA -- (MARKET WIRE) -- 11/12/2003-- Nuvation introduces the GEOS 2+2, a licensable FPGA IP Core that multiplexes and de-multiplexes two Gigabit Ethernet (GbE) data streams plus two Fast ...
Seeking Alpha

Microchip Slashes Time to Innovation with Industry’s Most Power-Efficient Mid-Range FPGA Industrial Edge Stack, More Core Library IP and Conversion Tools

CHANDLER, Ariz., June 05, 2023 (GLOBE NEWSWIRE) -- The new imperatives of the intelligent edge – power efficiency, security and reliability – are forcing system architects and design engineers to find ...
Embedded

Choosing hardware IP

As with any complex technology, embedded systems developers have many factors to consider when selecting a design partner in today's semiconductor market, particularly if planning to convert FPGAs to ...
Electronic Design

PRO DESIGN introduces FPGA SoC and IP prototyping platform

Munich, Germany. PRO DESIGN, a supplier of FPGA-based prototyping systems, today announced the launch of its three new proFPGA Zynq UltraScale+ FPGA modules, which offer an embedded processing ...