Clock gating is a well-understood power optimization technique employed in both ASIC and FPGA designs to eliminate unnecessary switching activity. This method usually requires that the designers add a ...

Flexibility is key to FPGA success, but speed is equally important. Achronix almost triples the throughput of the system by taking clock gating to the extreme. The Achronix Speedster FPGAs use a ...

This application note introduces FPGA designers to intelligent clock gating by describing clock gating support in the Xilinx design tools while supplying a detailed analysis of the impact of clock ...

Xilinx's latest incarnation of its Integrated Synthesis Environment, ISE Design Suite 12, now brings features such as ‘intelligent’ clock-gating technology to its line of FPGAs as well as a new ...